Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. In general, the use of FPGAs continues to grow at a rapid rate because FPGAs permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their reprogrammability. The capabilities of and specifications for XILINX FPGAs are set forth in "The Programmable Logic Data Book," published in 1998 by XILINX, Inc., the contents of which are incorporated herein by reference.
The field of reconfigurable computing has advanced steadily for the past decade, using FPGAs as the basis for high-performance reconfigurable systems. Run-Time Reconfigurable (RTR) systems distinguish themselves by performing circuit logic and routing customization at run-time. RTR systems using FPGAs are expected to result in systems that require less hardware, less software, and fewer input/output resources than traditional FPGA-based systems. However, scarcity of software that supports RTR is believed to be one reason that RTR has been outpaced by research in other areas of reconfigurable computing.
Whereas with traditional configuration of FPGAs the time taken to generate a programming bitstream is generally not real-time critical, with RTR systems, the time required to generate the programming bitstream may be critical from the viewpoint of a user who is waiting for the FPGA to be reconfigured. Thus, it may be acceptable to take hours to generate a programming bitstream using traditional configuration methods. In a run-time environment, however, it is expected that the reconfiguration process require no more than a few seconds or even a fraction of a second.
Reconfiguration of an FPGA may include reparameterizing various logic cores and rerouting connections between the logic cores. Parameterizable cores permit the user to enter information about the desired core, from which a customized circuit conforming to this information is constructed. An example of a parameterizable core is an adder core to produce an adder circuit. Example parameters include the size, for example, 4 bit, 8 bit, or 16 bit, and serial versus parallel.
Once reparameterized, the connections between cores and placement on the FPGA must be established. Routers in a traditional configuration process generally route connections for all the circuit elements. That is, these routers define connections for all the circuit elements in a design. Therefore, in an RTR environment, traditional reparameterization and routing methods are inappropriate given the real-time operating constraints.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.